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general description the max3301e/MAX3302E fully integrated usb on-the- go (otg) transceivers and charge pumps allow mobile devices such as pdas, cellular phones, and digital cameras to interface directly with usb peripherals and each other without the need of a host pc. use the max3301e/MAX3302E with an embedded usb host to directly connect to peripherals such as printers or external hard drives. the max3301e/MAX3302E integrate a usb otg trans- ceiver, a v bus charge pump, a linear regulator, and an i 2 c-compatible, 2-wire serial interface. an internal level shifter allows the max3301e/MAX3302E to interface with +1.65v to +3.6v logic supply voltages. the max3301e/MAX3302E? otg-compliant charge pump operates with +3v to +4.5v input supply voltages, and supplies an otg-compatible output on v bus while sourcing more than 8ma of output current. the max3301e/MAX3302E enable usb otg communi- cation from highly integrated digital devices that cannot supply or tolerate the +5v v bus levels that usb otg requires. the device supports usb otg session-request protocol (srp) and host-negotiation protocol (hnp). the max3301e/MAX3302E provide built-in ?5kv elec- trostatic-discharge (esd) protection for the v bus , id_in, d+, and d- terminals. the max3301e/MAX3302E are available in 25-bump chip-scale (ucsp), 28-pin tqfn, and 32-pin tqfn packages and operate over the extended -40 c to +85 c temperature range. applications mobile phones digital cameras pdas mp3 players features ? usb 2.0-compliant full-/low-speed otg transceivers ? ideal for usb on-the-go, embedded host, or peripheral devices ? ?5kv esd protection on id_in, v bus , d+, and d- terminals ? charge pump for v bus signaling and operation down to 3v ? internal v bus and id comparators ? internal switchable pullup and pulldown resistors for host/peripheral functionality ? i 2 c bus interface with command and status registers ? linear regulator powers internal circuitry and d+/d- pullup resistors ? support srp and hnp max3301e/MAX3302E usb on-the-go transceivers and charge pumps ________________________________________________________________ maxim integrated products 1 ordering information 19-3275; rev 2; 1/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part package size (mm) pin- package pkg code max3301e eba-t 2.5 x 2.5 25 ucsp b25-1 max3301eetj 5 x 5 32 tqfn-ep** t3255-4 MAX3302E eba-t* 2.5 x 2.5 25 ucsp b25-1 MAX3302Eeti 4 x 4 28 tqfn-ep** t2844-1 purchase of i 2 c components from maxim integrated products, inc. or one of its sublicensed associated companies, conveys a license under the philips i 2 c patent rights to use these compo- nents in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ucsp is a trademark of maxim integrated products, inc. note: all devices specified over the -40? to +85? operating range. ucsp bumps are in a 5 x 5 array. the ucsp package size is 2.5mm x 2.5mm x 0.62mm. requires solder temperature profile described in the absolute maximum ratings section. ucsp reli- ability is integrally linked to the user? assembly methods, circuit board material and environment. see the ucsp applications information section of this data sheet for more information. * future product?ontact factory for availability. ** ep = exposed paddle. part power-up state ? i 2 c addresses for special-function register 2 max3301e shutdown (sdwn = 1, bit 0 of special- function register 2) 16h, 17h MAX3302E operating ( sdwn = 1, bit 0 of special- function register 2) 10h, 11h, and 16h, 17h selector guide ? the max3301e powers up in its lowest power state and the MAX3302E powers up in the operational, vp/vm usb mode. pin configurations appear at end of data sheet.
max3301e/MAX3302E usb on-the-go transceivers and charge pumps 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc = +3v to +4.5v, v l = +1.65v to +3.6v, c flying = 100nf, c vbus = 1?, esr cvbus = 0.1 ? (max), t a = t min to t max , unless otherwise noted. typical values are at v cc = +3.7v, v l = +2.5v, t a = +25c.) (note 2) note 1: the ucsp package is constructed using a unique set of packaging techniques that impose a limit on the thermal profile the device can be exposed to during board-level solder attach and rework. this limit permits only the use of the solder profiles re com- mended in the industry-standard specification, jedec 020a, paragraph 7.6, table 3 for ir/vpr and convection reflow. preheating is required. hand or wave soldering is not allowed. stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. all voltages are referenced to gnd. v cc , v l .....................................................................-0.3v to +6v trm (regulator off or supplied by v bus ). .-0.3v to (v bus + 0.3v) trm (regulator supplied by v cc ) ...............-0.3v to (v cc + 0.3v) d+, d- (transmitter tri-stated) ...................................-0.3v to +6v d+, d- (transmitter functional)....................-0.3v to (v cc + 0.3v) v bus .........................................................................-0.3v to +6v id_in, scl, sda.......................................................-0.3v to +6v int , spd, reset , add, oe/int , rcv, vp, vm, sus, dat_vp, se0_vm ......................-0.3v to (v l + 0.3v) c+.............................................................-0.3v to (v bus + 0.3v) c-................................................................-0.3v to (v cc + 0.3v) short-circuit duration, v bus to gnd .........................continuous continuous power dissipation (t a = +70?) 5 x 5 ucsp (derate 12.2mw/? above +70?) ...........976mw 32-pin tqfn (5mm x 5mm x 0.8mm) (derate 21.3mw/? above +70?).............................................................1702mw 28-pin tqfn (4mm x 4mm x 0.8mm) (derate 20.8mw/? above +70?).............................................................1666mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? bump reflow temperature (note 1) infrared (15s) ...............................................................+200? vapor phase (20s) .......................................................+215? parameter sym b o l conditions min typ max units supply voltage v cc 3.0 4.5 v trm output voltage v trm 3.0 3.6 v logic supply voltage v l 1.65 3.60 v v l supply current i vl i 2 c interface in steady state 5 a v cc operating supply current i cc usb normal mode, c l = 50pf, device switching at full speed 10 ma vbus_drv = 1, i vbus = 0 1.4 2 v cc supply current during full- speed idle vbus_drv = 0, d+ = high, d- = low 0.5 0.8 ma v cc shutdown supply current i cc ( shdn ) 3.5 10 ? v cc interrupt shutdown supply current i cc ( ishdn ) id_in floating or high 20 30 ? v cc suspend supply current usb suspend mode, id_in floating or high 170 500 ? logic i/o rc v , d at_v p , s e 0_v m , int , oe / int , v p , v m outp ut h i g h v ol tag e v oh i out = 1ma (sourcing) v l - 0.4 v rcv, dat_vp, se0_vm, int , oe / int , vp, vm output low voltage v ol i out = 1ma (sinking) 0.4 v oe / int , spd, sus, reset , dat_vp, se0_vm input high voltage v ih 2/3 x v l v
max3301e/MAX3302E usb on-the-go transceivers and charge pumps _______________________________________________________________________________________ 3 dc electrical characteristics (continued) (v cc = +3v to +4.5v, v l = +1.65v to +3.6v, c flying = 100nf, c vbus = 1?, esr cvbus = 0.1 ? (max), t a = t min to t max , unless otherwise noted. typical values are at v cc = +3.7v, v l = +2.5v, t a = +25c.) (note 2) parameter sym b o l conditions min typ max units oe / int , spd, sus, reset dat_vp, se0_vm input low voltage v il 0.4 v add input high voltage v iha 2/3 x v l v add input low voltage v ila 1/3 x v l v input leakage current 1a transceiver specifications differential receiver input sensitivity |v d+ - v d- | 0.2 v differential receiver common- mode voltage 0.8 2.5 v single-ended receiver input low voltage v ild d+, d- 0.8 v single-ended receiver input high voltage v ihd d+, d- 2.0 v s i ng l e- e nd ed recei ver h yster esi s 0.2 v s i ng l e- e nd ed outp ut low v ol tag e v old d+, d-, r l = 1.5k ? from d+ or d- to 3.6v 0.3 v s i ng l e- e nd ed outp ut h i g h v ol tag e v ohd d+, d-, r l = 15k ? from d+ or d- to gnd 2.8 3.6 v off-state leakage current d+, d- 1a low steady-state drive 213 driver output impedance d+, d-, not including r ext high steady-state drive 213 ? esd protection (v bus , id_in, d+, d-) human body model 15 kv iec 61000-4-2 air-gap discharge 10 kv iec 61000-4-2 contact discharge 6kv thermal shutdown thermal shutdown low-to-high +160 o c thermal shutdown high-to-low +150 o c charge-pump specifications (vbus_drv = 1) v bus output voltage v bus 3v < v c c < 4.5v, c v bus = 10?, i v bus = 8m a 4.80 5.25 v v bus output current i vbus 8ma v bus output ripple i vbus = 8ma, c vbus = 10? 100 mv
max3301e/MAX3302E usb on-the-go transceivers and charge pumps 4 _______________________________________________________________________________________ dc electrical characteristics (continued) (v cc = +3v to +4.5v, v l = +1.65v to +3.6v, c flying = 100nf, c vbus = 1?, esr cvbus = 0.1 ? (max), t a = t min to t max , unless otherwise noted. typical values are at v cc = +3.7v, v l = +2.5v, t a = +25c.) (note 2) parameter sym b o l conditions min typ max units switching frequency f sw 390 khz v bus leakage voltage vbus_drv = 0 0.2 v v bus rise time c vbus = 10?, i vbus = 8ma, measured from 0 to +4.4v 100 ms v bus pulldown resistance vb u s_d is chrg = 1, vb us_d r v = 0, vb u s_chr g = 0 3.8 5 6.5 k ? v bus pullup resistance vb u s_chr g = 1, vb us_d r v = 0, vb u s_di schr g = 0 650 930 1250 ? v bus input impedance z invbus vb u s_d is chrg = 0, vb us_d r v = 0, vb u s_chr g = 0 40 70 100 k ? comparator specifications v b u s v al i d c om p ar ator thr eshol d v th-vbus 4.4 4.6 4.8 v v b u s v al i d c om p ar ator h yster esi s v hys-vbus 50 mv session-valid comparator threshold v th- sess_vld 0.8 1.4 2.0 v session-end comparator threshold v th- sess_end 0.2 0.5 0.8 v dp_hi comparator threshold 0.8 1.3 2.0 v dm_hi comparator threshold 0.8 1.3 2.0 v cr_int pulse width 750 ns cr_int comparator threshold 0.4 0.5 0.6 v id_in specifications id_in input voltage for car kit 0.2 x v cc 0.8 x v cc v id_in input voltage for a device 0.1 x v cc v id_in input voltage for b device 0.9 x v cc v id_in input impedance z id_in 70 100 130 k ? id_in input leakage current id_in = v cc -1 +1 ? id_in pulldown resistance id_pulldown = 1 150 300 ? terminating resistor specifications (d+, d-) d+ pulldown resistor dp_pulldown = 1 14.25 15 15.75 k ? d- pulldown resistor dm_pulldown = 1 14.25 15 15.75 k ? d+ pullup resistor dp_pullup = 1 1.425 1.5 1.575 k ? d- pullup resistor dm_pullup = 1 1.425 1.5 1.575 k ?
max3301e/MAX3302E usb on-the-go transceivers and charge pumps _______________________________________________________________________________________ 5 timing characteristics (v cc = +3v to +4.5v, v l = +1.65v to +3.6v, c flying = 100nf, c vbus = 1?, esr cvbus = 0.1 ? (max), t a = t min to t max , unless otherwise noted. typical values are at v cc = +3.7v, v l = +2.5v, t a = +25c.) (note 2) parameter sym b o l conditions min typ max units transmitter characteristics (full-speed mode) d+, d- rise time t r figures 2 and 5 4 20 ns d+, d- fall time t f figures 2 and 5 4 20 ns rise-/fall-time matching figures 2 and 5 (note 3) 90 110 % output-signal crossover voltage v crs_f figures 2, 6, and 7 (note 3) 1.3 2.0 v transmitter characteristics (low-speed mode) d+, d- rise time t r figures 2 and 5 75 300 ns d+, d- fall time t f figures 2 and 5 75 300 ns rise-/fall-time matching figures 2 and 5 80 125 % output-signal crossover voltage v crs_l figures 2, 6, and 7 1.3 2.0 v transmitter timing (full-speed mode) t plh low-to-high, figures 2 and 6 25 driver propagation delay (dat_vp, se0_vm to d+, d-) t phl high-to-low, figures 2 and 6 25 ns driver disable delay t pdz figures 1 and 8 25 ns driver enable delay t pzd figures 2 and 8 25 ns transmitter timing (low-speed mode) (low-speed delay timing is dominated by the slow rise and fall times.) speed-independent timing characteristics receiver disable delay t pvz figure 4 30 ns receiver enable delay t pzv figure 4 30 ns d+ pullup assertion time during hnp 3 s rcv rise time t r figures 3 and 5, c l = 15pf 4 ns rcv fall time t f figures 3 and 5, c l = 15pf 4 ns figures 3 and 10, |d+ - d-| to dat_vp 30 differential-receiver propagation delay t phl , t plh figures 3 and 9, |d+ - d-| to rcv 30 ns single-ended-receiver propagation delay t phl , t plh figures 3 and 9, d+, d- to dat_vp, se0_vm 30 ns interrupt propagation delay 100 ? v bus_chrg propagation delay dominated by the v bus rise time 0.2 ? time to exit shutdown 1s shutdown delay 10 ?
max3301e/MAX3302E usb on-the-go transceivers and charge pumps 6 _______________________________________________________________________________________ i 2 c-/smbus-compatible timing specifications (v cc = +3v to +4.5v, v l = +1.65v to +3.6v, c flying = 100nf, c vbus = 1?, esr cvbus = 0.1 ? (max), t a = t min to t max , unless otherwise noted. typical values are at v cc = +3.7v, v l = +2.5v, t a = +25c.) (note 2) parameter sym b o l conditions min typ max units serial clock frequency f scl 400 khz bus-free time between stop and start conditions t buf 1.3 ? start-condition hold time t hd_sta 0.6 ? stop-condition setup time t su_sto 0.6 ? clock low period t low 1.3 ? clock high period t high 0.6 ? data setup time t su_dat 100 ns data hold time t hd_dat (note 4) 0.9 ? rise time of sda and scl t r (note 5) 20 + 0.1 x c b 300 ns fall time of sda and scl t f measured from 0.3 x v l to 0.7 x v l (note 5) 300 ns capacitive load for each bus line c b 400 pf sda and scl i/o stage characteristics input-voltage low v il 0.3 x v l v input-voltage high v ih 0.7 x v l v sda output-voltage low v ol i sink = 3ma 0.4 v pulse width of suppressed spike t sp (note 6) 50 ns note 2: parameters are 100% production tested at +25 c. limits over temperature are guaranteed by design. note 3: guaranteed by bench characterization. limits are not production tested. note 4: a master device must provide a hold time of at least 300ns for the sda signal to bridge the undefined region of scl? falling edge. note 5: c b is the total capacitance of one bus line in pf, tested with c b = 400pf. note 6: input filters on sda, scl, and add suppress noise spikes of less than 50ns. smbus is a trademark of intel corporation.
driver propagation delay high-to-low (full-speed mode) max3301e toc09 4ns/div d+ 1v/div d- 1v/div dat_vp 1v/div driver propagation delay low-to-high (low-speed mode) max3301e toc08 100ns/div d- 1v/div d+ 1v/div dat_vp 1v/div driver propagation delay high-to-low (low-speed mode) max3301e toc07 100ns/div d+ 1v/div d- 1v/div dat_vp 1v/div time to exit shutdown max3301e toc05 4 s/div d- 1v/div d+ 1v/div scl 1v/div v bus during srp max3301e toc06 20ns/div v bus 1v/div v bus 1v/div c vbus > 96 f c vbus > 13 f time to enter shutdown max3301e toc04 100ns/div d+ 1v/div d- 1v/div scl 2v/div v bus output voltage vs. input voltage (v cc ) max3301e toc03 input voltage (v cc ) (v) v bus output voltage (v) 5.5 5.0 4.5 4.0 3.5 3.0 4.75 5.00 5.25 5.50 5.75 4.50 2.5 6.0 linear regulator powered by v cc i vbus = 8ma i vbus = 0 v bus output voltage vs. v bus output current max3301e toc02 v bus output current (ma) v bus output voltage (v) 25 20 15 10 5 4.25 4.50 4.75 5.00 5.25 5.50 4.00 030 v cc = 3.0v v cc = 4.2v linear regulator powered by v cc input current (i cc ) vs. v bus output current max3301e toc01 v bus output current (ma) input current (i cc ) (ma) 16 12 8 4 10 20 30 40 50 0 020 v cc = 3.3v v cc = 4.2v linear regulator powered by v cc max3301e/MAX3302E usb on-the-go transceivers and charge pumps _______________________________________________________________________________________ 7 t ypical operating characteristics (typical operating circuit, v cc = +3.7v, v l = +2.5v, c flying = 100nf, t a = +25?, unless otherwise noted.)
supply current vs. temperature max3301e toc15 temperature ( c) supply current (ma) 60 35 10 -15 0.2 0.4 0.6 0.8 1.0 0 -40 85 v bus off full-speed idle v cc = 3.3v v cc = 4.2v driver disable delay (low-speed mode) max3301e toc14 10ns/div d+ 1v/div d- 1v/div oe/int 1v/div driver enable delay (low-speed mode) max3301e toc13 100ns/div d- 1v/div d+ 1v/div c d+ = c d- = 400pf oe/int 1v/div driver disable delay (full-speed mode) max3301e toc12 10ns/div d+ 1v/div d- 1v/div oe/int 1v/div driver enable delay (full-speed mode) max3301e toc11 10ns/div d- 1v/div d+ 1v/div oe/int 1v/div driver propagation delay low-to-high (full-speed mode) max3301e toc10 4ns/div d- 1v/div d+ 1v/div dat_vp 1v/div max3301e/MAX3302E usb on-the-go transceivers and charge pumps 8 _______________________________________________________________________________________ t ypical operating characteristics (continued) (typical operating circuit, v cc = +3.7v, v l = +2.5v, c flying = 100nf, t a = +25?, unless otherwise noted.)
max3301e/MAX3302E usb on-the-go transceivers and charge pumps _______________________________________________________________________________________ 9 pin description pin MAX3302E 28-pin tqfn max3301e 32-pin tqfn ucsp name function 12 d2 dat_vp system-side data input/output. dat_vp is an input if oe / int is logic 0. dat_vp is an output if oe / int is logic 1. program the function of dat_vp with the dat_se0 bit (bit 2 of control register 1, see table 7). 2, 25 3, 29 d1, e3 v cc input power supply. connect a +3v to +4.5v supply to v cc and bypass to gnd with a 1? capacitor. the supply range enables direct powering from one li+ battery. 3, 9, 23 1, 4, 9, 12, 17, 25, 28 ? .c. no connection. not internally connected. 45 c1 c- charge-pump flying-capacitor negative terminal 56 c2 se0_vm system-side data input/output. se0_vm is an input if oe / int is logic 0. se0_vm is an output if oe / int is logic 1. program the function of se0_vm with the dat_se0 bit (bit 2 of control register 1, see table 7). 6, 18 7, 21 b1, c5 gnd ground 78a1 sda i 2 c-compatible serial data interface. open-drain data input/output. 810b2 scl i 2 c-compatible serial clock input 10 11 a2 oe / int o utp ut e nab l e. o e / int contr ol s t he i np ut or outp ut status of d at_v p /s e 0_v m and d + /d - . w hen o e / int i s l og i c 0, the d evi ce i s i n tr ansm i t m od e. w hen o e / int i s l og i c 1, the d evi ce i s i n r ecei ve m od e. when i n su sp end m od e, o e / int can b e p r og r am m ed to functi on as an i nter r up t outp ut that d etects the sam e i nter r up ts as int . the oe_i nt_en b i t ( b i t 5 of contr ol r eg i ster 1, see tab l e 7) enab l es and d i sab l es the i nter r up t ci r cui tr y of o e / int . the i r q _m od e b i t ( b i t 1 of sp eci al - functi on r eg i ster 2, see tab l e 15) p r og r am s the outp ut confi g ur ati on of int and o e / int as op en- d r ai n or p ush- p ul l . 11 13 a3 rcv d+ and d- differential receiver output. in receive mode (see table 4), when d+ is high and d- is low, rcv is high. in receive mode, when d+ is low and d- is high, rcv is low. rcv is low in suspend mode. 12 14 b3 spd speed-selector input. connect spd to gnd to select the low-speed data rate (1.5mbps). connect spd to v l to select the full-speed data rate (12mbps). disable the spd input by writing a 1 to spd_susp_ctl (bit 1 in special-function register 1, see table 14). the speed bit (bit 0 of control register 1, see table 7) determines the maximum data rate of the max3301e/MAX3302E when the spd input is disabled. 13 15 a4 v l system-side logic-supply input. connect to the system? logic-level power supply, +1.65v to +3.6v. this sets the maximum output levels of the logic outputs and the input thresholds of the logic inputs. bypass to gnd with a 0.1? capacitor. 14 16 a5 sus active-high suspend input. drive sus low for normal usb operation. drive sus high to enable suspend mode. rcv asserts low in suspend mode. disable the sus input by writing a 1 to spd_susp_ctl (bit 1 in special-function register 1, see table 14). the suspend bit (bit 1 of control register 1, see table 7) determines the operating mode of the max3301e/MAX3302E when the sus input is disabled.
max3301e/MAX3302E usb on-the-go transceivers and charge pumps 10 ______________________________________________________________________________________ pin description (continued) pin MAX3302E 28-pin tqfn max3301e 32-pin tqfn ucsp name function 15 18 b4 int active-low interrupt source. program the int output as push-pull or open- drain with the irq_mode bit (bit 1 of special-function register 2, see tables 15 and 16). 16 19 b5 reset active-low reset input. drive reset low to asynchronously reset the max3301e/MAX3302E. 17 20 c3 add i 2 c-interface address selection input. (see table 5.) 19 22 c4 id_in id input. id_in is internally pulled up to v cc . the state of id_in determines id bits 3 and 5 of the interrupt source register (see table 10). 20 23 d5 d- usb differential data input/output. connect d- to the d- terminal of the usb connector through a 27.4 ? 1% series resistor. 21 24 e5 d+ usb differential data input/output. connect d+ to the d+ terminal of the usb connector through a 27.4 ? 1% series resistor. 22 26 d4 vm single-ended receiver output. vm functions as a receiver output in all operating modes. vm duplicates d-. 24 27 e4 trm usb transceiver regulated output voltage. trm provides a regulated 3.3v output. bypass trm to gnd with a 1? ceramic capacitor installed as close to the device as possible. trm normally derives power from v cc . trm provides power to internal circuitry and provides the pullup voltage for the internal usb pullup resistor. do not use trm to power external circuitry. the reg_sel bit (bit 3 of special-function register 2, see table 15 and table 16) controls the trm power source with software. 26 30 d3 vp single-ended receiver output. vp functions as a receiver output in all operating modes. vp duplicates d+. 27 31 e2 v bus usb bus power. use v bus as an output to power the usb bus, or as an input to power the internal linear regulator. bits 5 to 7 of control register 2 (see table 8) control the charging and discharging functions of v bus . 28 32 e1 c+ charge-pump flying-capacitor positive terminal ep ep ep exposed paddle. connect to gnd or leave floating t est circuits and timing diagrams dut 27.4 ? 220 ? test point c l v d+/d- load for disable time (d+/d-) measurement v = 0 for t phz . v = v trm for t plz . c l = 50pf for full speed. c l = 200pf to 600pf for low speed. figure 1. load for disable time measurement dut 27.4 ? 15k ? test point c l d+/d- load for 1) enable time (d+/d-) measurement 2) dat_vp/seo_vm to d+/d- propagation delay 3) d+/d- rise/fall times c l = 50pf for full speed. c l = 200pf to 600pf for low speed. figure 2. load for enable time, transmitter propagation delay, and transmitter rise/fall times
max3301e/MAX3302E usb on-the-go transceivers and charge pumps ______________________________________________________________________________________ 11 t est circuits and timing diagrams (continued) 90% 10% v oh v ol t r t f figure 5. rise and fall times t plh d+ d- v crs_f , v crs_l v old v ohd v crs_f , v crs_l dat_vp se0_vm t phl figure 6. timing of dat_vp, se0_vm to d+, d- in vp_vm mode (dat_se0 = 0) t plh d+ d- v crs_f , v crs_l v old v ohd v crs_f , v crs_l dat_vp se0_vm t phl figure 7. timing of dat_vp, se0_vm to d+/d- in dat_se0 mode (dat_se0 = 1) t pdz d+ or d- v ol v old + 0.3v v ohd - 0.3v v oh v l v l / 2 v l / 2 0v t pzd oe/int figure 8. enable and disable timing t phl t phl t plh d+ d- rcv dat_vp se0_vm 3v 0v v l v l v l v l / 2 v l / 2 v l / 2 0v 0v 0v t plh t plh t phl d+/d- rise/fall times 8ns, v l = 1.8v, 2.5v, or 3.3v figure 9. d+/d- to rcv, dat_vp, se0_vm propagation delays (vp_vm mode) t phl d+ d- dat_vp se0_vm 3v 0v v l v l / 2 0v t plh d+/d- rise/fall times 8ns, v l = 1.8v, 2.5v, or 3.3v figure 10. d+/d- to dat_vp, se0_vm propagation delays (dat_se0 mode) dut test point c l rcv, vp, vm, dat_vp, seo_vm load for 1) d+/d- to rcv/vp/vm/dat_vp/seo_vm propagation delays 2) rcv/vp/vm/dat_vp/seo_vm rise/fall times (c l = 15pf) figure 3. load for receiver propagation delay and receiver rise/fall times dut 270 ? test point v = 2/3 x v l dat_vp seo_vm figure 4. load for dat_vp, se0_vm enable/disable time measurements
max3301e/MAX3302E usb on-the-go transceivers and charge pumps 12 ______________________________________________________________________________________ block diagram power block vp vm rcv gnd spd sus se0_vm dat_vp oe/int reset int level translator serial controller d- d+ v bus trm id_in c- c+ v cc v l car kit interrupt detector pullup/pulldown resistors linear regulator v bus comparators v bus charge pump id detector sda scl add diff tx diff rx se d+ se d- max3301e MAX3302E figure 11. block diagram
max3301e/MAX3302E usb on-the-go transceivers and charge pumps ______________________________________________________________________________________ 13 detailed description the usb otg specification defines a dual-role usb device that acts either as an a device or as a b device. the a device supplies power on v bus and initially serves as the usb host. the b device serves as the ini- tial peripheral and requires circuitry to monitor and pulse v bus . these initial roles can be reversed using hnp. the max3301e/MAX3302E combine a low- and full- speed usb transceiver with additional circuitry required by a dual-role device. the max3301e/MAX3302E employ flexible switching circuitry to enable the device to act as a dedicated host or peripheral usb transceiv- er. for example, the charge pump can be turned off and the internal regulator can be powered from v bus for bus-powered peripheral applications. the selector guide shows the differences between the max3301e and MAX3302E. the max3301e powers up in its lowest power state and must be turned on by set- ting the sdwn bit to 0. the MAX3302E powers up in the operational, vp/vm usb mode. this allows a micro- processor (?) to use the usb port for power-on boot- up, without having to access i 2 c. to put the MAX3302E into low-power shutdown, set the sdwn bit to 0. in the MAX3302E, special-function register 2 can be addressed at i 2 c register location 10h, 11h (as well as locations 16h, 17h) to support usb otg serial-interface engine (sie) implementations that are limited to i 2 c register addresses between 0h and 15h. transceiver the max3301e/MAX3302E transceiver complies with the usb version 2.0 specification, and operates at full- speed (12mbps) and low-speed (1.5mbps) data rates. set the data rate with the spd input. set the direction of data transfer with the oe/int input. alternatively, control transceiver operation with control register 1 (table 7) and special-function registers 1 and 2 (see tables 14, 15, and 16). level shifters internal level shifters allow the system-side interface to run at logic-supply voltages as low as +1.65v. interface logic signals are referenced to the voltage applied to the logic-supply voltage, v l . charge pump the max3301e/MAX3302E? otg-compliant charge pump operates with +3v to +4.5v input supply voltages (v cc ) and supplies a +4.8v to +5.25v otg-compatible output on v bus while sourcing the 8ma or greater out- put current that an a device is required to supply. connect a 0.1? flying capacitor between c+ and c-. bypass v bus to gnd with a 1f to 6.5? capacitor, in accordance with usb otg specifications. the charge pump can be turned off to conserve power when not used. control of the charge pump is set through the vbus_drv bit (bit 5) of control register 2 (see table 8). linear regulator (trm) an internal 3.3v linear regulator powers the transceiver and the internal 1.5k ? d+/d- pullup resistor. under the control of internal register bits, the linear regulator can be powered from v cc or v bus . the regulator power-supply settings are controlled by the reg_sel bit (bit 3) in special- function register 2 (tables 15 and 16). this flexibility allows the system designer to configure the max3301e/ MAX3302E for virtually any usb power situation. the output of the trm is not a power supply. do not use as a power source for any external circuitry. connect a 1.0? (or greater) ceramic or plastic capacitor from trm to gnd, as close to the device as possible. v bus level-detection comparators comparators drive interrupt source register bits 0, 1, and 7 (table 10) to indicate important usb otg v bus voltage levels: ? bus is valid (vbus_vld) usb session is valid (sess_vld) usb session has ended (sess_end) the vbus_valid comparator sets vbus_vld to 1 if v bus is higher than the v bus valid comparator threshold. the v bus valid status bit (vbus_vld) is used by the a device to determine if the b device is sinking too much current (i.e., is not supported). the session_valid comparator sets sess_vld to 1 if v bus is higher than the session valid comparator threshold. this status bit indicates that a data transfer session is valid. the session_end com- parator sets sess_end to 1 if v bus is higher than the figure 12. comparator network diagram v bus vbus_vld v th-vbus v th-sess_vld v th-sess_end sess_vld sess_end
max3301e/MAX3302E usb on-the-go transceivers and charge pumps 14 ______________________________________________________________________________________ mode i 2 c id_in sess_end comp sess _vld comp vbus_ vld comp cr_int comp dp_hi comp dm_hi comp trm tx diff rx se rx shutdown 1 ? xx x x x x xx xxx interrupt shutdown 2 ?? x ? xx ?? x xxx suspend 3 ?? ? ? ???? ? ? x ? normal operating table 1. functional blocks enabled during specific operating modes ? = enabled. x = disabled. 1. for the max3301e, enter shutdown mode by writing a 1 to sdwn (bit 0 of special-function register 2). for the MAX3302E, enter shutdown mode by writing a 0 to sdwn (bit 0 of special-function register 2). 2. enter interrupt shutdown mode by writing a 1 to int_sdwn (bit 0 of special-function register 1). 3. enter suspend mode by writing a 1 to spd_susp_ctl (bit 1 of special-function register 1) and suspend (bit 1 of control regist er 1), or by writing a 0 to spd_susp_ctl (bit 1 of special-function register 1) and driving sus high. session end comparator threshold. figure 12 shows the level-detector comparators. the interrupt-enable regis- ters (tables 12 and 13) determine whether a falling or rising edge of v bus asserts these status bits. id_in the usb otg specification defines an id input that determines which dual-role device is the default host. an otg cable connects id to ground in the connector of one end and is left unconnected in the other end. whichever dual-role device receives the grounded end becomes the a device. the max3301e/MAX3302E pro- vide an internal pullup resistor on id_in. internal com- parators detect if id_in is grounded or left floating. interrupt logic when otg events require action, the max3301e/ MAX3302E provide an interrupt output signal on int . alternatively, oe/int can be configured to act as an interrupt output while the device operates in usb sus- pend mode. program int and oe/int as open-drain or push-pull interrupts with irq_mode (bit 1 of special-func- tion register 2, see tables 15 and 16). v bus power control v bus is a dual-function port that powers the usb bus and/or provides a power source for the internal linear reg- ulator. the v bus power-control block performs the various switching functions required by an otg dual-role device. these actions are programmed by the system logic using bits 5 to 7 of control register 2 (see table 8) to: discharge v bus through a resistor provide power-on or receive power from v bus charge v bus through a resistor the otg supplement allows an a device to turn v bus off when the bus is not being used to conserve power. the b device can issue a request that a new session be started using srp. the b device must discharge v bus to a level below the session-end threshold (0.8v) to ensure that no session is in progress before initiating srp. setting bit 6 of control register 2 to 1, discharges v bus to gnd through a 5k ? current-limiting resistor. when v bus has discharged, the resistor is removed from the circuit by resetting bit 6 of control register 2. an otg a device is required to supply power on v bus . the max3301e/MAX3302E provide power to v bus from v cc or from the internal charge pump. set bit 5 in control register 2 to 1 in both cases. bit 5 in control register 2 controls a current-limited switch, preventing damage to the device in the event of a v bus short circuit. an otg b device (peripheral mode) can request a ses- sion using srp. one of the steps in implementing srp requires pulsing v bus high for a controlled time. a 930 ? resistor limits the current according to the otg specifi- cation. pulse v bus through the pullup resistor by assert- ing bit 7 of control register 2. prior to pulsing v bus (bit 7), a b device first connects an internal pulldown resis- tor to discharge v bus below the session-end threshold. the discharge current is limited by the 5k ? resistor and set by bit 6 of control register 2. an otg a device must
max3301e/MAX3302E usb on-the-go transceivers and charge pumps ______________________________________________________________________________________ 15 supply 5v power and at least 8ma on v bus . setting bit 5 of control register 2 turns on the v bus charge pump. operating modes the max3301e/MAX3302E have four operating modes to optimize power consumption. only the i 2 c interface remains active in shutdown mode, reducing supply cur- rent to 1?. the i 2 c interface, the id_in port, and the session-valid comparator all remain active in interrupt shutdown mode. rcv asserts low in suspend mode; how- ever, all other circuitry remains active. table 1 lists the active blocks?power in each of the operating modes. applications information data transfer transmitting data to the usb the max3301e/MAX3302E transceiver features two modes of transmission: dat_se0 or vp_vm (see table 3). set the transmitting mode with dat_se0 (bit 2 in control register 1, see table 7). in dat_se0 mode with oe/int low, dat_vp specifies data for the differential transceiv- er, and se0_vm forces d+/d- to the single-ended zero (se0) state. in vp_vm mode with oe/int low, dat_vp drives d+, and se0_vm drives d-. the differential receiver determines the state of rcv. receiving data from the usb the max3301e/MAX3302E transceiver features two modes of receiving data: dat_se0 or vp_vm (see table 4). set the receiving mode with dat_se0 (bit 2 in control register 1, see table 7). in dat_se0 mode with oe/int high, dat_vp is the output of the differential receiver and se0_vm indicates that d+ and d- are both logic-low. in vp_vm mode with oe/int high, dat_vp provides the input logic level of d+ and se0_vm pro- vides the input logic level of d-. the differential receiver determines the state of rcv. vp and vm echo d+ and d-, respectively. oe/int oe/int controls the direction of communication. oe/int can also be programmed to act as an interrupt output when in suspend mode. the output-enable portion con- trols the input or output status of dat_vp/se0_vm and d+/d-. when oe/int is a logic 0, dat_vp and se0_vm function as inputs to the d+ and d- outputs in a method depending on the status of dat_se0 (bit 2 in control reg- ister 1). when oe/int is a logic 1, dat_vp and se0_vm indicate the activity of d+ and d-. oe/int functions as an interrupt output when the max3301e/MAX3302E is in suspend mode and oe_int_en = 1 (bit 5 in control register 1, see table 7). in this mode, oe/int detects the same interrupts as int . set irq_mode (bit 1 in special-function register 2, see tables 15 and 16) to 0 to program oe/int as an open- drain interrupt output. set irq_mode to 1 to configure oe/int as a push-pull interrupt output. rcv rcv monitors d+ and d- when receiving data. rcv is a logic 1 for d+ high and d- low. rcv is a logic 0 for d+ low and d- high. rcv retains its last valid state when d+ and d- are both low (single-ended zero, or se0). rcv asserts low in suspend mode. table 4 shows the state of rcv. spd use hardware or software to control the slew rate of the d+ and d- terminals. the spd input sets the slew rate of the max3301e/MAX3302E when spd_susp_ctl (bit 1 in special-function register 1, see table 14) is 0. drive spd low to select low-speed mode (1.5mbps). drive spd high to select full-speed mode (12mbps). alternatively, when spd_susp_ctl (bit 1 of special-function register 1) is 1, software controls the slew rate. the spd input is ignored when using software to control the data rate. the speed bit (bit 0 of control register 1, see table 7) sets the slew rate when spd_susp_ctl = 1. sus use hardware or software to control the suspend mode of the max3301e/MAX3302E. set spd_susp_ctl (bit 1 of special-function register 1, see table 14) to 0 to allow the sus input to enable and disable the suspend mode of the max3301e/MAX3302E. drive sus low for normal operation. drive sus high to enable suspend mode. rcv asserts low in suspend mode while all other circuit- ry remains active. alternatively, when the spd_susp_ctl bit (bit 1 of special- function register 1) is set to 1, software controls the sus- pend mode. set the suspend bit (bit 1 of control register 1, see table 7) to 1 to enable suspend mode. set the suspend bit to 0 to resume normal operation. the sus input is ignored when using software to control suspend mode. the max3301e/MAX3302E must be in full-speed mode (spd = high or speed = 1) to issue a remote wake-up from the device when in suspend mode. reset the active-low reset input allows the max3301e/ MAX3302E to be asynchronously reset without cycling the power supply. drive reset low to reset the internal registers (see tables 7?6 for the default power-up states). drive reset high for normal operation.
max3301e/MAX3302E usb on-the-go transceivers and charge pumps 16 ______________________________________________________________________________________ 2-wire i 2 c-compatible serial interface a register file controls the various internal switches and operating modes of the max3301e/MAX3302E through a simple 2-wire interface operating at clock rates up to 400khz. this interface supports data bursting, where multiple data phases can follow a single address phase. uart mode set uart_en (bit 6 in control register 1) to 1 to place the max3301e/MAX3302E in uart mode. d+ transfers data to dat_vp and se0_vm transfers data to d- in uart mode. general-purpose buffer mode set gp_en (bit 7 in special-function register 1) and dat_se0 (bit 2 in control register 1) to 1, set uart_en (bit 6 in control register 1) to 0, and drive oe/int low to place the max3301e/MAX3302E in general-purpose buffer mode. control the direction of data transfer with dmi- nus_dir and dplus_dir (bits 3 and 4 of special-function register 1, see tables 2 and 14). serial addressing the max3301e/MAX3302E operate as a slave device that sends and receives control and status signals through an i 2 c -compatible 2-wire interface. the inter- face uses a serial data line (sda) and a serial clock line (scl) to achieve bidirectional communication between master(s) and slave(s). a master (typically a microcon- troller) initiates all data transfers to and from the max3301e/MAX3302E and generates the scl clock that synchronizes the data transfer (figure 13). the max3301e/MAX3302E sda line operates as both an input and as an open-drain output. sda requires a pullup resistor, typically 4.7k ? . the max3301e/ MAX3302E scl line only operates as an input. scl requires a pullup resistor if there are multiple masters on the 2-wire interface, or if the master in a single-master system has an open-drain scl output. each transmission consists of a start condition (see figure 14) sent by a master device, the max3301e/ MAX3302E 7-bit slave address (determined by the state of add), plus an r/ w bit (see figure 15), a register address byte, one or more data bytes, and a stop condi- tion (see figure 14). dplus_dir dminus_ dir direction of data transfer 00 dat_vp d+ se0_vm d- 01 dat_vp d+ se0_vm d- 10 dat_vp d+ se0_vm d- 11 dat_vp d+ se0_vm d- table 2. setting the direction of data transfer in general-purpose buffer mode sda scl t hd: sta t su: dat t hd: dat t su: sta t hd: sta t su: sto t buf t low t high t r t f start condition repeated start condition stop condition start condition figure 13. 2-wire serial-interface timing details
max3301e/MAX3302E usb on-the-go transceivers and charge pumps ______________________________________________________________________________________ 17 control pin/bit input output mode sus gp_en oe / int dat_se0 dat_vp se0_vm d+ d- description 000 1 0 0 0 1 000 1 1 0 1 0 000 1 0 1 0 0 functional dat_se0 000 1 1 1 0 0 000 0 0 0 0 0 000 0 1 0 1 0 000 0 0 1 0 1 functional vp_vm 000 0 1 1 1 1 u s b func ti onal m od e tr anscei ver and i 2 c i nter face ar e ful l y fu ncti onal 100 1 0 0 0 1 100 1 1 0 1 0 100 1 0 1 0 0 100 1 1 1 0 0 100 0 0 0 0 0 100 0 1 0 1 0 100 0 0 1 0 1 100 0 1 1 1 1 suspend 101 x x x driver is hi-z driver is hi-z usb suspend mode receiving 001 x x x driver is hi-z driver is hi-z see table 4 general- purpose buffer x1 01 see table 2 general-purpose buffer mode table 3. transmit mode sda scl s start condition p stop condition figure 14. start and stop conditions sda scl start msb 1 0 0 1 0 0a0 lsb ack r/w figure 15. slave address
max3301e/MAX3302E usb on-the-go transceivers and charge pumps 18 ______________________________________________________________________________________ control pin/bit inputs outputs mode sus (note 7) gp_en oe/int dat_se0 bi_di d+ d- dat_vp se0 _ vm rcv vp vm 001 11 00 last value of dat_vp 1 last value of rcv 001 11 10 101 001 11 01 000 001 11 11 undefined 0 undefined 101 11 00 010 101 11 10 100 101 11 01 000 functional dat_se0 101 11 11 100 001 01 00 00 last value of rcv 001 01 10 101 001 01 01 010 001 01 11 11 undefined 101 01 00 000 101 01 10 100 101 01 01 010 functional vp_vm 101 01 11 110 general- purpose buffer x1 xx x see table 2 0 transmitting (see table 3) xx0 xx 0 unidirectional (transmitter only) xxx x0 0 echo d+ echo d- table 4. receive mode note 7: enter suspend mode by driving sus high or by writing a 1 to suspend (bit 1 in control register 1), depending on the status of spd_susp_ctl in special-function register 1. x = don? care.
max3301e/MAX3302E usb on-the-go transceivers and charge pumps ______________________________________________________________________________________ 19 start and stop conditions both scl and sda assert high when the interface is not busy. a master device signals the beginning of a trans- mission with a start (s) condition by transitioning sda from high to low while scl is high. the master issues a stop (p) condition by transitioning sda from low to high while scl is high. the bus is then free for another trans- mission (see figure 14). bit transfer one data bit is transferred during each clock pulse. the data on sda must remain stable while scl is high (see figure 16). acknowledge the acknowledge bit (ack) is the 9th bit attached to any 8-bit data word. ack is always generated by the receiving device. the max3301e/MAX3302E generate an ack when receiving an address or data by pulling sda low during the ninth clock period. when transmit- ting data, the max3301e/MAX3302E wait for the receiv- ing device to generate an ack. monitoring ack allows for detection of unsuccessful data transfers. an unsuc- cessful data transfer occurs if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master should reat- tempt communication at a later time. slave address a bus master initiates communication with a slave device by issuing a start condition followed by the 7- bit slave address (see figure 15). when idle, the max3301e/MAX3302E wait for a start condition fol- lowed by its slave address. the lsb of the address word is the read/ write (r/ w ) bit. r/ w indicates whether the master is writing to or reading from the max3301e/MAX3302E (r/ w = 0 selects the write con- dition, r/ w = 1 selects the read condition). after receiving the proper address, the max3301e/ MAX3302E issue an ack. the max3301e/MAX3302E have two possible addresses (see table 5). address bits a6 through a1 are preset, while a reset condition or an i 2 c general call address loads the value of a0 from add. connect add to gnd to set a0 to 0. connect add to v l to set a0 to 1. this allows up to two max3301e? or two MAX3302E? to share the same bus. write byte format writing data to the max3301e/MAX3302E requires the transmission of at least 3 bytes. the first byte consists of the max3301e/MAX3302E? 7-bit slave address, fol- lowed by a 0 (r/ w bit). the second byte determines which register is to be written to. the third byte is the new data for the selected register. subsequent bytes are data for sequential registers. figure 18 shows the typical write byte format. read byte format reading data from the max3301e/MAX3302E requires the transmission of at least 3 bytes. the first byte con- sists of the max3301e/MAX3302E? slave address, fol- lowed by a 0 (r/ w bit). the second byte selects the register from which data is read. the third byte consists sda scl data line stable, data valid change of data allowed figure 16. bit transfer scl start condition s sda by transmitter sda by receiver clock pulse for acknowledgement 12 8 9 figure 17. acknowledge a register address (8 bits) msb lsb aap msb lsb d ata (8 bits) s slave address (7 bits) a6 a5 a4 a3 a2 a1 a0 0 r/w figure 18. write byte format
max3301e/MAX3302E usb on-the-go transceivers and charge pumps 20 ______________________________________________________________________________________ of the max3301e/MAX3302E? slave address, followed by a 1 (r/ w bit). the master then reads one or more bytes of data. figure 19 shows the typical read byte format. burst-mode write byte format the max3301e/MAX3302E allow a master device to write to sequential registers without repeatedly sending the slave address and register address each time. the master first sends the slave address, followed by a 0 to write data to the max3301e/MAX3302E. the max3301e/MAX3302E send an acknowledge bit back to the master. the master sends the 8-bit register address and the max3301e/MAX3302E return an acknowledge bit. the master writes a data byte to the selected register and receives an acknowledge bit if a supported register address has been chosen. the reg- ister address increments and is ready for the master to send the next data byte. the max3301e/MAX3302E send an acknowledge bit after each data byte. if an unsupported register is selected, the max3301e/ MAX3302E send a nack to the master and the register index does not increment (see figure 20). s slave address (7 bits) a6 a5 a4 a3 a2 a1 a0 0 a register address (k) (8 bits) msb lsb aa msb lsb data (k) (8 bits) data (k+1) (8 bits) a data (k+2) (8 bits) msb lsb aa msb lsb data (k+n) (8 bits) msb lsb p s slave address (7 bits) a6 a5 a4 a3 a2 a1 a0 0 a unsupported register address (k) (8 bits) msb lsb ana msb lsb data (k) (8 bits) max3301e/MAX3302E recognizes its address max3301e/MAX3302E sends an ack max3301e/MAX3302E recognizes a write to an unsupported location, then sends a nack r/w r/w figure 20. burst-mode write byte format s slave address (7 bits) a6 a5 a4 a3 a2 a1 a0 0 0 0 a register address (8 bits) msb lsb a rs slave address (7 bits) a6 a5 a4 a3 a2 a1 a0 1 1 0 0 a d ata (8 bits) msb lsb na p r/w r/w figure 19. read byte format r/ w : read/write (r/ w = 1: read; r/ w = 0: write) s: start condition rs: repeated start condition p: stop condition a: acknowledge bit from the slave na: not-acknowledged bit from the master blank: master transmission
max3301e/MAX3302E usb on-the-go transceivers and charge pumps ______________________________________________________________________________________ 21 s slave address (7 bits) a6 a5 a4 a3 a2 a1 a0 0 a register address (k) (8 bits) msb lsb a a data (k) (8 bits) msb lsb aa msb lsb data (k+1) (8 bits) s slave address (7 bits) a6 a5 a4 a3 a2 a1 a0 0 a unsupported register address (k) (8 bits) msb lsb a max3301e/MAX3302E recognize their address max3301e/MAX3302E sends an ack ack from master p s slave address (7 bits) a6 a5 a4 a3 a2 a1 a0 1 a data (k+3) (8 bits) msb lsb ana msb lsb data (k+n) (8 bits) data (k+2) (8 bits) msb lsb p p s slave address (7 bits) a6 a5 a4 a3 a2 a1 a0 1 a unsupported register address (k) (8 bits) ?all 0's returned msb lsb a r/w r/w r/w r/w figure 21. burst-mode read byte format table 5. i 2 c slave address map address bits add input a 6 a 5 a 4 a 3 a 2 a 1 a 0 gnd (0) 0101100 v l (1) 0101101
max3301e/MAX3302E usb on-the-go transceivers and charge pumps 22 ______________________________________________________________________________________ register memory address description vendor id 00h, 01h read only. the contents of registers 00h and 01h are 6ah and 0bh, respectively. product id 02h, 03h read only. the contents of registers 02h and 03h are 01h and 33h, respectively. control 1 04h (set) 05h (clear) sets operating modes, maximum data rate, and direction of data transfer. control 2 06h (set) 07h (clear) controls d+/d- pullup/pulldown resistor connections, id_in state, and v bus behavior. interrupt source 08h (read) read only. unused* 09h not used. interrupt latch 0ah (set) 0bh (clear) indicates which interrupts have occurred. interrupt-enable falling edge 0ch (set) 0dh (clear) enables interrupts for high-to-low transitions. interrupt-enable rising edge 0eh (set) 0fh (clear) enables interrupts for low-to-high transitions. unused*/special function 2 10h (set) 11h (clear) max3301e: not used. MAX3302E: alternate register addresses for special-function register 2. this register is also accessible from 16h and 17h. special function 1 12h (set) 13h (clear) enables hardware/software control of the max3301e's behavior, interrupt activity, and operating modes. revision id 14h, 15h read only. the contents of registers 14h and 15h are 77h and 41h, respectively. special function 2 16h (set) 17h (clear) sets operating modes, int output configuration, d+/d- behavior in audio mode, and trm source. unused* 18h?h not used. table 6. register map burst-mode read byte format the max3301e/MAX3302E allow a master device to read data from sequential registers with the burst-mode read byte protocol (see figure 21). the master device first sends the slave address, followed by a 0. the max3301e/MAX3302E then sends an acknowledge bit. next, the master sends the register address to the max3301e/MAX3302E, which then generates another acknowledge bit. the master then sends a stop (p) con- dition to the max3301e/MAX3302E. next, the master sends a start condition, followed by the max3301e/ MAX3302E? slave address, and then a 1 to indicate a read command. the max3301e/MAX3302E then sends data to the master device, one byte at a time. the master sends an acknowledge bit to the max3301e/ MAX3302E after each data byte, and the register address of the max3301e/MAX3302E increments after each byte. this continues until the master sends a stop (p) condition. if an unsupported register address is encountered, the max3301e/MAX3302E send a byte of zeros. registers control registers there are two read/write control registers. control regis- ter 1 (table 7) sets operating modes, sets the data rate, and controls the direction of data transfer. control regis- ter 2 (table 8) connects the d+/d- pullup or pulldown resistors, sets the v bus charge/discharge conditions, and grounds id_in. the control registers have two addresses that implement write-one-set and write-one- clear features for each of these registers. writing a 1 to the set address sets that bit to 1. writing a 1 to the clear address resets that bit to 0. writing a 0 to either address has no effect on the bits. * when writing to an unused register, the device generates a nack and the register index does not increment.
max3301e/MAX3302E usb on-the-go transceivers and charge pumps ______________________________________________________________________________________ 23 bit number symbol operation value at power-up 0 speed s et to 0 for l ow - sp eed ( 1.5m b p s) m od e. s et to 1 for ful l - sp eed ( 12m b p s) m od e. thi s b i t chang es the d ata r ate onl y i f sp d _susp _ctl = 1 i n sp eci al - functi on r eg i ster 1. 0 1 suspend set to 0 for normal operating mode. set to 1 for suspend mode. this bit changes the operating mode only if spd_susp_ctl = 1 in sp eci al - functi on r eg i ster 1. 0 2 dat_se0 set to 0 for vp_vm usb mode. set to 1 for dat_se0 usb mode. 0 3 not used. 0 4 bdis_acon_en enables the transceiver (when configured as an a device) to connect its pullup resistor if the b device disconnect is detected during hnp. set to 0 to disable this feature. set to 1 to enable this feature. 0 5 oe_int_en set to 0 to disable the interrupt output circuitry of oe / int . set to 1 to enable the interrupt output circuitry of oe / int . 0 6 uart_en set to 0 to disable uart mode. set to 1 to enable uart mode. this bit overrides the settings of dminus_dir, dplus_dir, and gp_en bits. 0 7 not used. 0 table 7. control register 1 description (write to address 04h to set, write to address 05h to clear) bit number symbol operation value at power-up 0 dp_pullup s et to 0 to d i s connect the p ul lup resi stor to d+ . set to 1 to connect the pul l up r esi stor to d +. 0 1 dm_pullup s et to 0 to d i s connect the p ul l up r esi stor to d - . s et to 1 to connect the p ul l up r esi stor to d - .0 2 dp_pulldown set to 0 to disconnect the pulldown resistor to d+. set to 1 to connect the pulldown resistor to d+. 1 3 dm_pulldown set to 0 to disconnect the pulldown resistor to d-. set to 1 to connect the pulldown resistor to d-. 1 4 id_pulldown set to 0 to allow id_in to float. set to 1 to connect id_in to gnd. 0 5 vbus_drv s et to 0 to tur n v b u s off. s et to 1 to d r i ve v b u s thr oug h a l ow i m p ed ance ( see n ote 8) . 0 6 vbus_dischrg set to 0 to disconnect the v bus discharge resistor. set to 1 to connect the v bus discharge resistor (see note 8). 0 7 vbus_chrg set to 0 to disconnect the v bus charge resistor. set to 1 to connect the v bus charge resistor (see note 8). 0 table 8. control register 2 description (write to address 06h to set, write to address 07h to clear) note 8: to prevent a high-current state where the transceiver is both sourcing current to v bus and sinking current from v bus , the fol- lowing logic is used to set bits 5, 6, and 7 of control register 2: setting vbus_drv clears vbus_dischrg and vbus_chrg setting vbus_dischrg clears vbus_drv and vbus_chrg, unless vbus_drv is set with the same command, in which case vbus_drv clears the other bits ? etting vbus_chrg clears vbus_drv and vbus_dischrg, unless either of these bits are set with the same command, as shown in tab le 9
max3301e/MAX3302E usb on-the-go transceivers and charge pumps 24 ______________________________________________________________________________________ set command (address 06h) behavior of max3301e/MAX3302E vbus_drv vbus_dischrg vbus_chrg vbus_drv vbus_dischrg vbus_chrg 1xx 1 0 0 01x 0 1 0 001 0 0 1 00 0 not affected not affected not affected table 9. v bus control logic bit number symbol contents 0 vbus_vld logic 1 if v bus > v bus valid comparator threshold. 1 sess_vld logic 1 if v bus > session valid comparator threshold. 2 dp_hi logic 1 if v d+ > dp_hi comparator threshold (d+ assertion during data line pulsing through srp method). 3 id_gnd logic 1 if v id_in < 0.1 x v cc . 4 dm_hi logic 1 if v d- > dm_hi comparator threshold (d- assertion during data line pulsing through srp method). 5 id_float logic 1 if v id_in > 0.9 x v cc . 6 bdis_acon logic 1 if bdis_acon_en = 1 and the max3301e/MAX3302E assert dp_pullup after detecting a b device disconnect during hnp. 7 cr_int_sess_end log i c 1 i f v bu s < sess_end com p ar ator thr es hol d , or i f v d + > cr _i nt com p ar ator thr eshol d ( 0.4v to 0.6v ) , d ep end i ng on the val ue of i nt_sour ce ( b i t 5 of sp eci al - f uncti on r eg i ster 1, see tab l e 14) . table 10. interrupt source register (address 08h is read only) interrupt registers four registers control all interrupt behavior of the max3301e/MAX3302E. a source register (table 10) indicates the current status of the various interrupt sources. an interrupt latch register (table 11) indicates which interrupts have occurred. an interrupt-enable low and interrupt-enable high register enable interrupts on rising or falling (or both) transitions. tables 10?3 pro- vide the bit configurations for the various interrupt regis- ters. the interrupt latch, interrupt-enable low, and interrupt-enable high registers have two addresses that implement write- one-set and write-one-clear features for each of these registers. writing a 1 to the set address sets that bit to 1. writing a 1 to the clear address resets that bit to 0. writing a 0 to either address has no effect on the bits. special-function registers tables 14, 15, and 16 describe the special-function registers. the special-function registers have two addresses that implement write-one-set and write-one- clear features for each of these registers. writing a 1 to the set address sets that bit to 1. writing a 1 to the clear address resets that bit to 0. writing a 0 to either address has no effect on the bits. special-function reg- ister 1 determines whether hardware or software con- trols the maximum data rate and suspend behavior, sets the direction of data transfer, and toggles general- purpose buffer mode. special-function register 2 enables shutdown mode, configures the interrupt out- put as open-drain or push-pull, sets the trm power source, and controls the d+/d- connections for audio mode. table 15 depicts the special-function register 2 for the max3301e and table 16 depicts the special- function register 2 for the MAX3302E. the max3301e powers up in its lowest power state and must be turned on by setting the sdwn bit to 0. the MAX3302E powers up in the operational, vp/vm usb mode. this allows a ? to use the usb port for power- on boot-up, without having to access i 2 c. to put the MAX3302E into low-power shutdown, set the sdwn bit to 0. the MAX3302E also has special-function register 2 mapped to two i 2 c register addresses. in the MAX3302E, special-function register 2 can be x = don? care.
max3301e/MAX3302E usb on-the-go transceivers and charge pumps ______________________________________________________________________________________ 25 bit number symbol contents value at power-up 0 vbus_vld vb us_vl d asser ts i f a tr ansi ti on occur s on thi s co nd i ti on and the ap p r op r i ate i nter r up t- hi g h or i nter r up t- l ow enab l e b i t i s set. s ee tab l es 10, 12, and 13. 0 1 sess_vld sess_vl d asser ts i f a tr ansi ti on occur s on thi s co nd i ti on and the ap p r op r i ate i nter r up t- hi g h or i nter r up t- l ow enab l e b i t i s set. s ee tab l es 10, 12, and 13. 0 2 dp_hi d p _hi asser ts i f a tr ansi ti on occur s on thi s co nd i ti on and the ap p r op r i ate i nter r up t- hi g h or i nter r up t- l ow enab l e b i t i s set. s ee tab l es 10, 12, and 13. 0 3 id_gnd i d _g nd asser ts i f a tr ansi ti on occur s on thi s c ond i ti on and the ap p r op r i ate i nter r up t- hi g h or i nter r up t- l ow enab l e b i t i s set. s ee tab l es 10, 12, and 13. 0 4 dm_hi d m _hi asser ts i f a tr ansi ti on occur s on thi s co nd i ti on and the ap p r op r i ate i nter r up t- hi g h or i nter r up t- l ow enab l e b i t i s set. s ee tab l es 10, 12, and 13. 0 5 id_float i d _fl oat asser ts i f a tr ansi ti on occur s on thi s co nd i ti on and the ap p r op r i ate i nter r up t- hi g h or i nter r up t- l ow enab l e b i t i s set. s ee tab l es 10, 12, and 13. 0 6 bdis_acon b d i s_a con asser ts i f a tr ansi ti on occur s on thi s co nd i ti on and the ap p r op r i ate i nter r up t- hi g h or i nter r up t- l ow enab l e b i t i s set. s ee tab l es 10, 12, and 13. 0 7 cr_int_sess_end cr _i nt _sess_end asser ts i f a tr ansi ti on oc cur s on thi s co nd i ti on and the ap p r op r i ate i nter r up t- hi g h or i nter r up t- l ow enab l e b i t i s set. s ee tab l es 10, 12, and 13. 0 table 11. interrupt latch register description (write to address 0ah to set, write to address 0bh to clear) bit number symbol contents value at power-up 0 vbus_vld s et to 0 to d i sab l e the vb u s_vld i nter rup t for a hig h- to- l ow transiti on. s et to 1 to enab l e the vb u s_vld i nter rup t for a hig h- to- l ow transiti on. s ee tab l es 10 and 11. 0 1 sess_vld s et to 0 to d i sab l e th e sess_vld i nter rup t for a hig h- to- l ow transiti on. s et to 1 to enab l e t he sess_vld i nter rup t for a hig h- to- l ow transiti on. s ee tab l es 10 and 11. 0 2 dp_hi s et to 0 to d i sab l e the d p _hi interr up t for a hi g h-to- low tr ansi ti on. se t to 1 to enab l e the d p _hi interr up t for a hi g h-to- low tr ansi ti on. see tab l es 10 and 11. 0 3 id_gnd s et to 0 to d i sab l e the i d _g nd i nter r upt for a hi g h- to-l ow tr ansi tion. s et to 1 to enab l e the i d _g nd i nter r upt for a hi g h- to-l ow tr ansi tion. s ee tab les 10 and 11. 0 4 dm_hi s et to 0 to d i sab l e the d m _hi interr up t for a hi g h-to- low tr ansi ti on. se t to 1 to enab l e the d m _hi interr up t for a hi g h-to- low tr ansi ti on. see tab l es 10 and 11. 0 5 id_float s et to 0 to d i sab l e the i d _fl oat i nter rup t for a hig h- to- l ow transiti on. s et to 1 to enab l e the i d _fl oat i nter rup t for a hig h- to- l ow transiti on. s ee tab l es 10 and 11. 0 6 bdis_acon s et to 0 to d i sab l e the b d i s_acon interr up t for a hi g h-to- low tr ansi ti on. se t to 1 to enab l e the b d i s_acon interr up t for a hi g h-to- low tr ansi ti on. see tab l es 10 and 11. 0 7 cr_int_sess_end s et to 0 to d i sab l e the cr _i nt _sess_end i nter r up t for a hi g h- to- l ow tr ansi ti on. s et to 1 to enab l e the cr _i nt _sess_end i nter r up t for a hi g h- to- l ow tr ansi ti on. s ee tab l es 10 and 11. 0 table 12. interrupt-enable low register (write to address 0ch to set, write to address 0dh to clear)
addressed at i 2 c register location 10h, 11h (as well as locations 16h, 17h) to support usb otg sie implemen- tations that are limited to i 2 c register addresses between 0h and 15h. id and manufacturer register address map table 17 provides the contents of the id registers of the max3301e/MAX3302E. addresses 00h and 01h com- prise the vendor id registers. addresses 02h and 03h comprise the product id registers. addresses 14h and 15h comprise the revision id registers. audio car kit many cell phones are required to interface to car kits. depending upon the car kit, the interface to the phone may be required to support any or all of the following functions: audio input audio output charging control and status d+ and d- of the max3301e/MAX3302E go to a high- impedance state when in shutdown mode, allowing external signals (including audio) to be multiplexed onto these lines. external components external resistors two external resistors (27.4 ? ?%) are required for usb connection. install one resistor in series between d+ of the max3301e/MAX3302E and d+ of the usb connector. install the other resistor in series between d- of the max3301e/MAX3302E and d- of the usb con- nector (see the typical operating circuit ). external capacitors five external capacitors are recommended for proper operation. install all capacitors as close to the device as possible. decouple v l to gnd with a 0.1? ceramic capacitor. bypass v cc to gnd with a 1? ceramic capacitor. bypass trm to gnd with a 1f (or greater) ceramic or plastic capacitor. connect a 100nf flying capacitor between c+ and c- for the charge pump (see the typical operating circuit ). bypass v bus to gnd with a 1? to 6.5? ceramic capacitor in accordance with usb otg specifications. esd protection to protect the max3301e/MAX3302E against esd, d+, d-, id_in, and v bus , have extra protection against stat- ic electricity to protect the device up to ?5kv. the esd structures withstand high esd in all states; normal oper- max3301e/MAX3302E usb on-the-go transceivers and charge pumps 26 ______________________________________________________________________________________ bit number symbol contents value at power-up 0 vbus_vld s et to 0 to d i sab l e the vb u s_vld i nter rup t for a l ow - to- hi gh transiti on. s et to 1 to enab l e the vb u s_vld i nter rup t for a l ow - to- hi gh transiti on. s ee tab l es 10 and 11. 0 1 sess_vld s et to 0 to d i sab l e th e sess_vld i nter rup t for a l ow - to- hi gh transiti on. s et to 1 to enab l e t he sess_vld i nter rup t for a l ow - to- hi gh transiti on. s ee tab l es 10 and 11. 0 2 dp_hi s et to 0 to d i sab l e the d p _hi i nter r up t for a l ow - to- hi g h tr ansi ti on. s et to 1 to enab l e the d p _hi i nter r up t for a l ow - to- hi g h tr ansi ti on. s ee tab l es 10 and 11. 0 3 id_gnd s et to 0 to d i sab l e the i d _g nd i nter r up t for a l ow - to- hi g h tr ansi ti on. s et to 1 to enab l e the i d _g nd i nter r up t for a l ow - to- hi g h tr ansi ti on. s ee tab l es 10 and 11. 0 4 dm_hi s et to 0 to d i sab l e the d m _hi i nter r up t for a l ow - to- hi g h tr ansi ti on. s et to 1 to enab l e the d m _hi i nter r up t for a l ow - to- hi g h tr ansi ti on. s ee tab l es 10 and 11. 0 5 id_float s et to 0 to d i sab l e the i d _fl oat i nter r up t for a l ow - to- hi g h tr ansi ti on. s et to 1 to enab l e the i d _fl oat i nter r up t for a l ow - to- hi g h tr ansi ti on. s ee tab l es 10 and 11. 0 6 bdis_acon s et to 0 to d i sab l e the b d i s_acon interr up t for a low - to- hig h tr ansi ti on. se t to 1 to enab l e the b d i s_acon interr up t for a low - to- hig h tr ansi ti on. see tab l es 10 and 11. 0 7 cr_int_sess_end s et to 0 to d i sab l e the cr _i nt _sess_end i nter r up t for a l ow - to- hi g h tr ansi ti on. s et to 1 to enab l e the cr _i nt _sess_end i nter r up t for a l ow - to- hi g h tr ansi ti on. s ee tab l es 10 and 11. 0 table 13. interrupt-enable high register (write to address 0eh to set, write to address 0fh to clear)
max3301e/MAX3302E usb on-the-go transceivers and charge pumps ______________________________________________________________________________________ 27 bit number symbol contents value at power-up 0i nt_sdwn s et to 0 for nor m al op er ati on. s et to 1 to enter i nter r up t shutd ow n m od e. the i 2 c i nter f ace and i nter r up t sour ces r em ai n acti ve, w hi l e al l other ci r cui tr y i s off. 0 1 spd_susp_ctl s et to 0 to contr ol the m ax 3301e /m ax 3302e b ehavi or w i th s p d and s u s . s et to 1 to contr ol the m ax 3301e /m ax 3302e b ehavior w i th the sp eed and susp end b i ts i n contr ol r eg i ster 1 (see tab l e 7) . 0 2 bi_di set to 0 to transfer data from dat_vp and se0_vm to d+ and d-, respectively. dat_vp and se0_vm are always inputs when this bit is 0. set to 1 to control the direction of data transfer with oe / int . 1 3 dminus_dir set to 0 to transfer data from se0_vm to d-. set to 1 to transfer data from d- to se0_vm. ensure that gp_en = 1, dat_se0 = 1, uart_en = 0, and oe / int = low to activate this function. 0 4 dplus_dir set to 0 to transfer data from dat_vp to d+. set to 1 to transfer data from d+ to dat_vp. ensure that gp_en = 1, dat_se0 = 1, uart_en = 0, and oe / int = low to activate this function. 0 5 int_source set to 0 to use cr_int as the interrupt source for bit 7 of the interrupt source register. set to 1 to use sess_end as the interrupt source for bit 7 of the interrupt source register (see table 10). 0 6 sess_end session end comparator status (read only). sess_end = 0 when v bus > sess_end threshold. sess_end = 1 when v bus < sess_end threshold. 7 gp_en set to 0 to disable general-purpose buffer mode. set to 1 to enable general- purpose buffer mode. 0 table 14. special-function register 1 (write to address 12h to set, write to address 13h to clear) bit number symbol contents value at power-up 0 sdwn set to 0 for normal operation. set to 1 to enable shutdown mode. only the i 2 c interface remains active in shutdown. 1 1 irq_mode set to 0 to set int and oe / int as open-drain outputs. set to 1 to set int and oe / int as push-pull outputs. 0 2 xcvr_input_disc s et to 0 to l eave the d + /d - si ng l e- end ed r ecei ver i np uts co nnected . s et to 1 to d i scon nect the d + /d - r e cei ver i np uts to r ed uce p ow er consum p ti on i n aud i o m od e. 0 3 reg_sel set to 0 to power trm from v cc . set to 1 to power trm from v bus .0 4? reserved. set to 0 for normal operation. 0000 table 15. max3301e special-function register 2 (write to address 16h to set, write to address 17h to clear) ation, suspend mode, interrupt shutdown, and shut- down. for the esd structures to work correctly, connect a 1? or greater capacitor from trm to gnd and from v bus to gnd. esd protection can be tested in various ways; the d+, d-, id_in, and v bus inputs/outputs are characterized for protection to the following limits: 15kv using the human body model 6kv using the iec 61000-4-2 contact discharge method 10kv using the iec 61000-4-2 air-gap discharge method note: sess_end value at power-up is dependent on the voltage at v bus .
max3301e/MAX3302E esd performance depends on a variety of conditions. contact maxim for a reliability report that documents test setup, methodology, and results. human body model figure 22 shows the human body model and figure 23 shows the current waveform it generates when dis- charged into a low impedance. this model consists of a 100pf capacitor charged to the esd voltage of interest, which is then discharged into the test device through a 1.5k ? resistor. iec 61000-4-2 the iec 61000-4-2 standard covers esd testing and performance of finished equipment; it does not specifi- cally refer to integrated circuits. the max3301e/ MAX3302E helps the user design equipment that meets level 3 of iec 61000-4-2, without the need for additional esd-protection components. the major difference between tests done using the human body model and iec 61000-4-2 is a higher peak current in iec 61000-4-2, due to the fact that series resistance is lower in the iec 61000-4-2 model. hence, the esd-withstand voltage measured to iec 61000-4-2 is generally lower than that measured using the human body model. figure 24 shows the iec 61000-4-2 model. the air-gap discharge test involves approaching the device with a charged probe. the contact discharge method connects the probe to the device before the probe is energized. figure 25 shows the iec 61000-4-2 current waveform. layout considerations the max3301e/MAX3302E high operating frequency makes proper layout important to ensure stability and maintain the output voltage under all loads. for best performance, minimize the distance between the bypass capacitors and the max3301e/MAX3302E. use symmetric trace geometry from d+ and d- to the usb connector. ucsp applications information for the latest application details on ucsp construction, dimensions, tape carrier information, pc board tech- niques, bump-pad layout, and the recommended reflow temperature profile, as well as the latest information on reliability testing results, refer to the application note: ucsp? wafer-level chip-scale package available on maxim? website at www.maxim-ic.com/ucsp. usb on-the-go transceivers and charge pumps 28 ______________________________________________________________________________________ bit number symbol contents value at power-up 0 sdwn set to 0 to enable shutdown mode. set to 1 for normal operation. only the i 2 c interface remains active in shutdown. 1 1 irq_mode set to 0 to set int and oe / int as open-drain outputs. set to 1 to set int and oe / int as push-pull outputs. 0 2 xcvr_input_disc s et to 0 to l eave the d+ /d - si ng l e-end ed r e cei ver inp uts connected . s et to 1 to d i s connect the d + /d- r e cei ver inp uts to r educe p ow er consump ti on i n audi o mod e. 0 3 reg_sel set to 0 to power trm from v cc . set to 1 to power trm from v bus .0 4? reserved. set to 0 for normal operation. 0000 table 16. MAX3302E special-function register 2 (write to address 10h or 16h to set, write to address 11h or 17h to clear) register address contents 00h 6ah vendor id 01h 0bh 02h 01h product id 03h 33h 14h 77h revision id 15h 41h table 17. id registers
max3301e/MAX3302E usb on-the-go transceivers and charge pumps ______________________________________________________________________________________ 29 charge-current- limit resistor discharge resistance storage capacitor c s 100pf r c 1m ? r d 1.5k ? high- voltage dc source device under test figure 22. human body esd test modes i p 100% 90% 36.8% t rl time t dl current waveform peak-to-peak ringing (not drawn to scale) i r 10% 0 0 amperes figure 23. human body model current waveform charge-current- limit resistor discharge resistance storage capacitor c s 150pf r c 50m ? to 100m ? r d 330 ? high- voltage dc source device under test figure 24. iec 61000-4-2 esd test model i 100% 90% 10% t r = 0.7ns to 1ns i peak 60ns 30ns t figure 25. iec 61000-4-2 current waveform chip information process: bicmos
max3301e/MAX3302E usb on-the-go transceivers and charge pumps 30 ______________________________________________________________________________________ 32 31 30 29 28 27 26 9 10 11 12 13 14 15 18 19 20 21 22 23 24 7 6 5 4 3 2 1 max3301e tqfn (5mm x 5mm) top view dat_vp n.c. v cc n.c. c- se0_vm exposed paddle gnd 8 sda c+ v bus vp v cc n.c. trm vm 25 n.c. d+ d- id_in gnd add reset int 17 n.c. v l spd 16 sus rcv n.c. oe/int scl n.c. max3301e/MAX3302E ucsp (2.5mm x 2.5mm) oe/int rcv v l sus sda a scl spd int reset gnd b se0_vm add id_in gnd c- c dat_vp vp vm d- v cc d v bus v cc trm d+ c+ e 1 23 45 MAX3302E top view 26 27 25 24 10 9 11 v cc c- se0_vm gnd sda 12 dat_vp d- gnd add d+ reset int 12 v cc 4567 20 21 19 17 16 15 vp v bus spd rcv oe/int n.c. n.c. id_in 3 18 28 8 c+ scl trm 23 13 v l n.c. 22 14 sus vm exposed paddle tqfn (4mm x 4mm) bottom view pin configurations
max3301e/MAX3302E usb on-the-go transceivers and charge pumps ______________________________________________________________________________________ 31 max3301e MAX3302E asic dat_vp se0_vm rcv vp vm sda scl sus spd v l(i/o) add gnd trm d+ d- 27.4 ? 27.4 ? id_in v bus c+ c- otg connector v bus d+ d- id gnd v l v cc v l v cc *usb otg specifications limit the total capacitance on v bus from 1 f (min) to 6.5 f (max) for a dual-role device. 0.1 f oev/int int reset 1 f c flying 0.1 f 1 f c vbus * 4.7 f t ypical operating circuit
max3301e/MAX3302E usb on-the-go transceivers and charge pumps 32 ______________________________________________________________________________________ pa cka ge information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) qfn thin.eps d2 (nd-1) x e e d c pin # 1 i.d. (ne-1) x e e/2 e 0.08 c 0.10 c a a1 a3 detail a e2/2 e2 0.10 m c a b pin # 1 i.d. b 0.35x45 d/2 d2/2 l c l c e e l c c l k l l detail b l l1 e aaaaa marking i 1 2 21-0140 package outline, 16, 20, 28, 32, 40l thin qfn, 5x5x0.8mm -drawing not to scale- l e/2
max3301e/MAX3302E usb on-the-go transceivers and charge pumps ______________________________________________________________________________________ 33 common dimensions max. exposed pad variations d2 nom. min. min. e2 nom. max. ne nd pkg. codes 1. dimensioning & tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. angles are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 6. nd and ne refer to the number of terminals on each d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 9. drawing conforms to jedec mo220, except exposed pad dimension for t2855-3 and t2855-6. notes: symbol pkg. n l1 e e d b a3 a a1 k 10. warpage shall not exceed 0.10 mm. jedec 0.70 0.80 0.75 4.90 4.90 0.25 0.25 0 -- 4 whhb 4 16 0.35 0.30 5.10 5.10 5.00 0.80 bsc. 5.00 0.05 0.20 ref. 0.02 min. max. nom. 16l 5x5 l 0.30 0.50 0.40 -- - -- - whhc 20 5 5 5.00 5.00 0.30 0.55 0.65 bsc. 0.45 0.25 4.90 4.90 0.25 0.65 - - 5.10 5.10 0.35 20l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. -- - whhd-1 28 7 7 5.00 5.00 0.25 0.55 0.50 bsc. 0.45 0.25 4.90 4.90 0.20 0.65 - - 5.10 5.10 0.30 28l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. -- - whhd-2 32 8 8 5.00 5.00 0.40 0.50 bsc. 0.30 0.25 4.90 4.90 0.50 - - 5.10 5.10 32l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. 0.20 0.25 0.30 down bonds allowed yes 3.10 3.00 3.20 3.10 3.00 3.20 t2055-3 3.10 3.00 3.20 3.10 3.00 3.20 t2055-4 t2855-3 3.15 3.25 3.35 3.15 3.25 3.35 t2855-6 3.15 3.25 3.35 3.15 3.25 3.35 t2855-4 2.60 2.70 2.80 2.60 2.70 2.80 t2855-5 2.60 2.70 2.80 2.60 2.70 2.80 t2855-7 2.60 2.70 2.80 2.60 2.70 2.80 3.20 3.00 3.10 t3255-3 3 3.20 3.00 3.10 3.20 3.00 3.10 t3255-4 3 3.20 3.00 3.10 no no no no yes yes yes yes 3.20 3.00 t1655-3 3.10 3.00 3.10 3.20 no no 3.20 3.10 3.00 3.10 t1655n-1 3.00 3.20 3.35 3.15 t2055-5 3.25 3.15 3.25 3.35 yes 3.35 3.15 t2855n-1 3.25 3.15 3.25 3.35 no 3.35 3.15 t2855-8 3.25 3.15 3.25 3.35 yes 3.20 3.10 t3255n-1 3.00 no 3.20 3.10 3.00 l 0.40 0.40 ** ** ** ** ** ** ** ** ** ** ** ** ** ** see common dimensions table 0.15 11. marking is for package orientation reference only. i 2 2 21-0140 package outline, 16, 20, 28, 32, 40l thin qfn, 5x5x0.8mm -drawing not to scale- 12. number of leads shown are for reference only. 3.30 t4055-1 3.20 3.40 3.20 3.30 3.40 ** yes 0.05 0 0.02 0.60 0.40 0.50 10 ----- 0.30 40 10 0.40 0.50 5.10 4.90 5.00 0.25 0.35 0.45 0.40 bsc. 0.15 4.90 0.25 0.20 5.00 5.10 0.20 ref. 0.70 min. 0.75 0.80 nom. 40l 5x5 max. 13. lead centerlines to be at true position as defined by basic dimension "e", 0.05. t1655-2 ** yes 3.20 3.10 3.00 3.10 3.00 3.20 t3255-5 yes 3.00 3.10 3.00 3.20 3.20 3.10 ** exceptions package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max3301e/MAX3302E usb on-the-go transceivers and charge pumps 34 ______________________________________________________________________________________ package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 24l qfn thin.eps package outline, 21-0139 2 1 e 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm package outline, 21-0139 2 2 e 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm
max3301e/MAX3302E usb on-the-go transceivers and charge pumps maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 35 2006 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 25l, ucsp.eps h 1 1 21-0096 package outline, 5x5 ucsp

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